Tempe, Arizona - April 14, 2009 - Devices with low gate charge and low drain voltage, present several challenges in determining gate charge quantities. Traditional waveform analysis techniques can have difficulty finding very short plateau regions and due to the inherent high gain of some devices, the sharp transitions of current at turn off may introduce distortions in the gate waveform in the area of the Qgd / Qgs knee region.

ITC has analyzed many of these "non-ideal" waveforms, and as a result has developed a new method and analysis algorithm. The results of analyzing a typical "non-ideal" gate waveform from actual test data are shown in the graph below.

According to the test procedure for gate charge (JESD24-2) the slope of the plateau region when using a high impedance drain load can be considered to be zero. Determining the plateau first simplifies the process of using a best fit algorithm to find the two slopes in the waveform. The calculations can then be performed to determine the charge values for each section, and also to perform the stray capacitance correction. This new analysis method provides more accurate results in less time for a wider range of devices.

For a more detailed explanation of ITC's Gate Charge test capability, to arrange to have samples tested or to schedule an equipment demonstration please email Mark McLaren at markm@inttechcorp.com